This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-038469, filed Feb. 16, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device for use in a power-switching device such as an insulated gate bipolar transistor (IGBT) and a power MOSFET and a method of manufacturing the same.
A semiconductor device having a punch-through structure (referred to as a PT structure hereinafter) is generally used in a power-switching device. If the power-switching device is an IGBT, the PT structure causes an Nxe2x88x92 layer to be completely depleted when the highest voltage is applied to the IGBT.
FIG. 12 exemplifies an IGBT having a PT structure. As FIG. 12 shows, a Pxe2x88x92-type diffusion layer 42 is formed on the surface of an Nxe2x88x92 layer 41 formed by epitaxial growth (hereinafter referred to as an Nxe2x88x92 epi-wafer), and an N+-type diffusion layer 43 and a P+-type diffusion layer 44 are formed on the layer 42. A gate electrode 47 is formed in the Nxe2x88x92 epi-wafer 41 with a gate insulation film 46 interposed therebetween, and an emitter electrode 61 is selectively formed above the Nxe2x88x92 epi-wafer 41. Furthermore, an N+-type buffer layer 62 (referred to as an N+ buffer layer hereinafter) is formed on the underside of the Nxe2x88x92 epi-wafer 41, and a P+-type anode layer 63 (referred to as a P+ anode layer hereinafter) is formed on the underside of the layer 62. A collector electrode 64 is also formed on the underside of the P+ anode layer 63. If the IGBT is a product having a withstanding voltage of 1200V, the thickness of the Nxe2x88x92 epi-wafer 41 is 100 xcexcm, that of the N+ buffer layer 62 is 5 xcexcm, and that of the P+ anode layer 63 is 400 xcexcm.
In the IGBT having such a PT structure, a depletion layer grows from the Pxe2x88x92-type diffusion layer 42 to the Nxe2x88x92 epi-wafer 41 when a switch is off. The N+ buffer layer 62 suppresses the growth of the depletion layer and prevents the depletion layer from contacting the P+ anode layer 63.
Since the IGBT includes the P+ anode layer 63, a number of holes are implanted into the Nxe2x88x92 epi-wafer 41 from the P+ anode layer 63, thereby increasing an energy loss when the switch is off (referred to as Eoff hereinafter). In order to reduce the Eoff, the N+ buffer layer 62 having a thickness of 5 xcexcm or more is provided, and an electron beam and a photon radiation are emitted to cause crystal defects.
However, a wafer used in the PT structure corresponds to the Nxe2x88x92 epi-wafer 41 that grows epitaxially. The IGBT having a PT structure therefore has the problem that the manufacturing cost of the wafer is high.
A Raw wafer, which is not processed, can be considered to be an inexpensive wafer used in place of the epi-wafer 41, and an IGBT having a non-punch-through structure (referred to as an NPT structure hereinafter) using the Raw wafer is realized. The NPT structure causes an Nxe2x88x92 layer to be depleted only 70% to 80% when the highest voltage is applied to the IGBT, unlike the PT structure.
FIG. 13 exemplifies an IGBT having an NPT structure. In FIG. 13, the same constituting elements as those of the IGBT having a PT structure shown in FIG. 12 are indicated by the same reference numerals.
In the NPT structure, an Nxe2x88x92 layer 71 is formed in place of the Nxe2x88x92 epi-wafer 41 and the N+ buffer layer 62 of the PT structure. If the IGBT is a product having a withstanding voltage of 1200V, the thickness of the Nxe2x88x92 layer 71 is 200 xcexcm and that of the P+ anode layer 63 is 400 xcexcm. In the IGBT shown in FIG. 13, the constituents other than the Nxe2x88x92 layer 71 are the same as those of the IGBT shown in FIG. 12 and thus their descriptions are omitted.
In the IGBT having an NPT structure, the Nxe2x88x92 layer 71 should be formed up to such a desired thickness as to prevent a depletion layer, which expands when the highest voltage is applied to the IGBT, from reaching a collector electrode 64. More specifically, if the IGBT is a product having a withstanding voltage of 1200V, the thickness of the Nxe2x88x92 layer 71 should be 200 xcexcm to obtain a cutoff voltage when a switch is off, whereas in the PT structure the thickness of the Nxe2x88x92 epi-wafer 41 has only to be about 100 xcexcm. In other words, the NPT structure necessitates an Nxe2x88x92 layer which is twice as thick as that of the PT structure in order to create the same withstanding voltage. The NPT structure therefore has the problem that power consumption increases more greatly than that in the PT structure when a switch is on.
One therefore requires that an IGBT (not shown) having a PT structure using a Raw wafer be realized and, in other words, one requires an IGBT in which an N+ buffer layer and a P+ anode layer are formed on the underside of a Raw wafer. The PT structure using a Raw wafer decreases a manufacturing cost and produces a device that can suppress power consumption more greatly than that having an NPT structure. The N+ buffer layer should be formed up to such a thickness that a depletion layer is stopped from reaching an anode layer by a reverse withstanding voltage to create a device withstanding voltage and reduce the Eoff.
In the IGBT having a PT structure using a Raw wafer, however, a surface structure (a P+-type diffusion layer, etc.) of the wafer is difficult to form after the wafer is thinned. Thus, after the surface structure of the wafer is formed, the wafer is thinned and then the underside structure (an N+ buffer layer, etc.) is formed by ion implantation, annealing and the like. Taking into consideration that heat damage is caused to the surface of the wafer, there is a limit to diffusion temperatures. In other words, it was difficult to form an N+ buffer layer having a thickness (e.g., 5 xcexcm or more) necessary for generating a device withstanding voltage and reducing the Eoff. It has been therefore thought that an IGBT having a PT structure using a Raw wafer is difficult to achieve.
As described above, the IGBT having a PT structure using an epi-wafer has the problem that the epi-wafer increases in manufacturing cost. The IGBT having an NPT structure using a Raw wafer has the problem that power consumption increases when a switch is on.
Furthermore, the IGBT having a PT structure using a Raw wafer, which is proposed to overcome the above problems, has the problem that an N+ buffer layer having a desired thickness is difficult to form because heat damage is caused to the surface and restricts the formation of an underside structure.
Consequently, it is difficult to form an IGBT capable of reducing in manufacturing cost and suppressing power consumption.
The present invention has been developed in order to resolve the above problems and its object is to provide a semiconductor device capable of reducing manufacturing costs and suppressing power consumption and a method of manufacturing the same.
To attain the above object, the present invention has the following structures:
A first semiconductor device of the present invention comprises a first diffusion region of a second conductivity type formed on a surface of a semiconductor substrate of a first conductivity type, a second diffusion region of the first conductivity type selectively formed on a surface of the first diffusion region, a gate electrode formed in or on the semiconductor substrate with a gate insulation film interposed therebetween, an emitter electrode electrically insulated from the gate electrode and selectively formed on the semiconductor substrate, an inactive region of the first conductivity type formed on an underside of the semiconductor substrate, the inactive region having incompletely activated ions, an active region of the first conductivity type formed on an underside of the inactive region, the active region having highly activated ions, an anode layer of the second conductivity type formed on an underside of the active region, and a collector electrode formed on an underside of the anode layer.
A second semiconductor device of the present invention comprises a first diffusion region of a second conductivity type formed on a surface of a semiconductor substrate of a first conductivity type, a second diffusion region of the first conductivity type selectively formed on a surface of the first diffusion region, a gate electrode formed in or on the semiconductor substrate with a gate insulation film interposed therebetween, a source electrode electrically insulated from the gate electrode and selectively formed on the semiconductor substrate, an inactive region of the first conductivity type formed on an underside of the semiconductor substrate, the inactive region having incompletely activated ions, an active region of the first conductivity type formed on an underside of the inactive region, the active region having highly activated ions, and a drain electrode formed on an underside of the active region.
A third semiconductor device of the present invention comprises a first diffusion region of a second conductivity type formed on a surface of a semiconductor substrate of a first conductivity type, a second diffusion region of the first conductivity type selectively formed on a surface of the first diffusion region, a gate electrode formed in or on the semiconductor substrate with a gate insulation film interposed therebetween, a source electrode electrically insulated from the gate electrode and selectively formed on the semiconductor substrate, an inactive region of the first conductivity type formed on an underside of the semiconductor substrate, the inactive region having incompletely activated ions, and a drain electrode formed on an underside of the inactive region.
In the first to third semiconductor devices, the electrical activation rate X of the ions of the inactive region is expressed as 1%xe2x89xa6Xxe2x89xa630%.
In the first to third semiconductor devices, the integrated carrier concentration Y of the inactive region is expressed as 1xc3x971012/cm2xe2x89xa6Yxe2x89xa61xc3x971015/cm2.
In the first semiconductor device, the carrier concentration of the active region is higher than that of the inactive region, and a carrier concentration of the anode layer is higher than that of the active region. The ratio Z of carrier concentration of the anode layer to that of the active region is given by 1 less than Z less than 100.
In the second semiconductor device, the carrier concentration of the active region is higher than that of the inactive region.
A method of manufacturing a semiconductor device of the present invention, comprises the steps of forming a first diffusion region of a second conductivity type on a surface of a semiconductor substrate of a first conductivity type, selectively forming a second diffusion region of the first conductivity type on a surface of the first diffusion region, forming a gate electrode in or on the semiconductor substrate with a gate insulation film interposed therebetween, selectively forming an emitter electrode on the semiconductor substrate, polishing an underside of the semiconductor substrate, forming an active region of the first conductivity type on the underside of the semiconductor substrate and an anode layer of the second conductivity type on an underside of the active region by heat treatment after ions are implanted into the underside of the semiconductor substrate, the active region having highly activated ions, forming a collector electrode on an underside of the anode layer after the ions are implanted into the underside of the semiconductor substrate, and forming an inactive region of the first conductivity type between the semiconductor substrate and the active region by heat treatment, the inactive region having incompletely activated ions.
The present invention thus provides a semiconductor device capable of reducing manufacturing costs and suppress power consumption and a method of manufacturing the same.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.